As a method for manufacturing an SOI wafer, especially for manufacturing a thin-film SOI wafer that can improve the performance of an advanced integrated circuit, a method for delaminating an ion-implanted wafer after bonding to manufacture an SOI wafer (an ion-implantation delamination method: technology that is also called the Smart Cut method (a registered trademark)) has been received attention. This ion-implantation delamination method is technology that forms an oxide film on at least one of two silicon wafers, implants gas ions such as hydrogen ions or rare gas ions from an upper surface of one silicon wafer (a bond wafer), forms a micro bubble layer (a sealed layer) in the interior of the wafer, then adhering the surface from which the ions are implanted to the other silicon wafer (a base wafer) through the oxide film, subsequently performs a heat treatment (a delamination heat treatment) to delaminate the one wafer (the bond wafer) into a thin film-form by making the micro bubble layer be a cleaved surface, and further performs a heat treatment (a bonding heat treatment) to strengthen the bonding, thereby manufacturing an SOI wafer (see Patent Document 1). In this stage, the cleaved surface (a delaminated surface) becomes a surface of an SOI layer, and an SOI wafer having a thin SOI film with high thickness uniformity can be obtained relatively easily.
In this case, the peripheral portion of the SOI wafer contains a portion that cannot be bonded, and this portion is generally called a terrace. When this terrace width is large, the periphery removing region of an SOI wafer have to be set to wider than in the usual mirror polished wafer (PW). On the other hand, when the terrace width is small, even the periphery can be used for forming a device, and the effective area of a wafer can be enlarged. Accordingly, an SOI wafer with small terrace width is desirable. The terrace width is mainly determined by a roll-off shape of a wafer, that is, a sag shape on the periphery. When the sag becomes larger, the portion that cannot be bonded is widened (i.e., the terrace width is enlarged).
Patent Document 2 discloses a method for reducing the chamfer width on the a bonding surface side of both wafers in order to obtain an SOI wafer having an SOI layer which contain no or reduced periphery removing region (terrace portion) by using an ion-implantation delamination method. Patent Document 3 discloses a method for bonding in which the chamfer width is set to 100 μm or less in order to reduce the non-bonded portion of the periphery of a semiconductor bonded wafer to make the terrace portion thereof extremely small.